As scaling of devices on metal-oxide-semiconductor (MOS) integrated circuits (ICs) shrinks device dimensions, increased electrostatic discharge (ESD) sensitivity results. It is consequently increasingly important to provide ESD protection circuits to protect the devices and circuits on the IC against ESD-related damage. The ESD robustness of commercial IC products is generally needed to be higher than 2 kV in the Human-Body-Model (HBM) ESD stress. While withstanding ESD overstress, it is desired that on-chip ESD protection circuits also have relatively small dimensional requirements to save semiconductor (e.g., silicon) chip area.
For example, USB 2.0 devices require low total capacitance CTOT—ESD<250 fF with a clamping voltage of the ESD protection of Vhold>Vsupply (typically 5V) to minimize interference with normal operations of the device. A small area “footprint” is also desired for on-chip ESD protection circuits. This is typically achieved with Silicon Controlled Rectifiers (SCRs), which, however, feature Vhold<Vsupply. These conflicting needs must be simultaneously met.